Question about verilog

[EDA_hg81]

made program with Xilinx ISE.

using wires to connect modules. what is the possible reasons why some FF/latch inside modules are not connected?

Thank you.

 

[zeeshanzia84]

post your code

 

[EDA_hg81]

The code is as following:

module CPU ( SPI_IN, ROW, COL );
input SPI_IN;
output [10:0]ROW;
output [10:0]COL;

reg [10:0]ROW_REG;
reg [10:0]COL_REG:

assign ROW = ROW_REG;
assign COL = COL_REG;

always @ (posedge SPI_CE)

case (SPI_COMMAND)

8'h26:
ROW_REG <= SPI_DATA_IN[10:0];
8'h28
COL_REG <= SPI_DATA_IN[10:0];
end
end module

Why ROW is connected in code?

But Col is not connected?

What is the possible reason?

Thank you.

 

[Vasilis]

To connect modules you should create instances of each one and put as parameters the variables you want.A reason why some FF/latch inside modules are not connected may be the size of a bus you may try to connect to a module.
In te code you have posted you have a few syntax errors.(missing ';' and ':').

 

[prathulla]

Checkthe book palnitker

 

[EDA_hg81]

I have put my code in the following link:



Thank you for any your suggestions.

 

[bansalr]

For the Refresh_COL_REG <= SPI_DATA_IN[10:0];

The SPI_DATA_IN is not assigned anywhere this signal is only used. So synthesis will trim this logic.

For the BUWREN. Check the usgae of begin and end

 

[EDA_hg81]

But why Refresh_ROW_REG is not trimed?

 

[EDA_hg81]

How can I fix :

Refresh_COL_REG <= SPI_DATA_IN[10:0];

Thank you.

 

[tkbits]

Use the COL_reg in Line_Buf. Or connect Refresh_COL to output pins.

 

[freeinthewind]

i think maybe you have problem about clock.

 

[Matrix_YL]

The code is as following:

module CPU ( SPI_IN, ROW, COL );
input SPI_IN;
output [10:0]ROW;
output [10:0]COL;

reg [10:0]ROW_REG;
reg [10:0]COL_REG:

assign ROW = ROW_REG;
assign COL = COL_REG;

always @ (posedge SPI_CE)

case (SPI_COMMAND)

8'h26:
ROW_REG <= SPI_DATA_IN[10:0];
8'h28
COL_REG <= SPI_DATA_IN[10:0];
end
end module

Why ROW is connected in code?

But Col is not connected?

What is the possible reason?

Thank you.

Are you sure it's SPI_CE(no declamation in module ) instead of SPI_IN?
I fell SPI_CE is enable signal instead of clk signal ,am right ?