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question about verilog simulation lib

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lightcloud

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Hi,
I use smic13 artisanmemory compiler generating single port and dual port register file and use generated verilog lib to make rtl simulation,the simulation process is not continued.so I change them with smic18 memory verilog mode,the result is right.Through analyzing,find when at a certain time the data wrote to the memory changed to X state,so the result is wrong,how to solve it;
if I make netlist simulation at zero delay mode with ncverilog ,the change to standard cell verilog lib is required,such as delete delay information?and front simulation library have any difference with back simulation library?
thanks a lot
best regards
 

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