question about verilog behavioral model

[alerta]

the following is a pragraf of Verilog Behavioral Model of Synchronous Mobile SDRAM


task write_task;
begin
begin: write_op
integer i, j, k;
reg [`BIT] tmp_reg;
integer bank_id;
reg [8*8:1] str;

if(~burst_type)
increment_read;
else
interleave_read;

begin: write_seq
for(i = 0; i < WBL; i = i+1)
begin // { for loop
begin
.......


I don't know the meaning of "write_op " and "write_seq", they seems no use,
are they only a mark ,or the standard?
who can tell me,thanks

 

[asic_bh]

"write_op " and "write_seq", are just the name given to the block of code (from begin to end). This is useful when u want disable the execution of that block of code which is done by saying disable block name. That can be enabled again

 

[tigerajs]

it is a process

 

[naveen reddy]

hai
This is the concept of named blocks in verilog
You can name a block and disable a named block

eg >> begin:write_op
write_op is the name given to this particular block

You can have any number of named blocks in your design with a unique name

 

[anilkumarv]

They are basically the names given to the particular block

 

[chviswanadh]

Those are just the labels of the process. In small codes one may not find it much useful but while writing large code where u might have many process blocks (which may look similar) it is of great use to give the labels. these are for users reference only.