Question about using dual port BRAM with Spartan-II

[m_kartik]

Hi, I'm using Spartan-II FPGA and i have Dual port BRAM in my design.
i'm writing on Port B and reading from port A.
Please refer the waveform - the data 0x0E00 is available in the next clock cycle after ENA is asserted.
But i need to get the data on the same clock cycle, when ENA is high. Is it possibile to do it?
Someone plz help me....

 

[Elephantus]

Re: BRAM Spartan-II

Hi. If you are using RAMB4_S16 blockram from spartan II, you apparently cannot have the output in the same clock cycle the write enable strobe is asserted as the BRAM has a synchronous write, the ENA will get sampled on the next rising edge of clock.

Also, why do you need this? In a synchronous design, the data will get sampled on the next rising edge of clock on the other side, you simply need to delay the ENA signal for 1 clk period(provided that both sides are using the same clock speed).

I might be able to help more if you could post more about what are you trying to achieve.

 

[m_kartik]

Re: BRAM Spartan-II

Hi. If you are using RAMB4_S16 blockram from spartan II, you apparently cannot have the output in the same clock cycle the write enable strobe is asserted as the BRAM has a synchronous write, the ENA will get sampled on the next rising edge of clock.

Also, why do you need this? In a synchronous design, the data will get sampled on the next rising edge of clock on the other side, you simply need to delay the ENA signal for 1 clk period(provided that both sides are using the same clock speed).

I might be able to help more if you could post more about what are you trying to achieve.

Thanks for the reply. I'm using RAMB4_S16_S16 BRAM from Spartan II. The thing is i've a FIFO which is made up of BRAM. The output of the BRAM/FIFO is going to PCI Interface, which is expecting the data on the same clock cycle, the ENA is asserted. Since the ENA is generated by the PCI Core, i can't get this signal 1 cycle earlier.

 

[nand_gates]

Re: BRAM Spartan-II

Can't you tie ENA to '1' permenently in ur design??

 

[Elephantus]

Re: BRAM Spartan-II

The PCI core therefore expects to have the data ready when the ENA signal which it produces is high, to sample it on the next rising edge of clock? This seems highly unusual for a synchronous design.
If it is absolutely necessary, you could either try inverting the port A clock, or use a 180deg phase shifted clock (respective to CLKA from your example),CLKA180, to clock the port A.
In that case, the ENA will be sampled in the BRAM on the rising edge of CLKA180, which corresponds to the falling edge of CLKA, and data will be present on the DOA output for the rising edge of CLKA.

 

[m_kartik]

Re: BRAM Spartan-II

The PCI core therefore expects to have the data ready when the ENA signal which it produces is high, to sample it on the next rising edge of clock? This seems highly unusual for a synchronous design.
If it is absolutely necessary, you could either try inverting the port A clock, or use a 180deg phase shifted clock (respective to CLKA from your example),CLKA180, to clock the port A.
In that case, the ENA will be sampled in the BRAM on the rising edge of CLKA180, which corresponds to the falling edge of CLKA, and data will be present on the DOA output for the rising edge of CLKA.

I was also thinking of inverting the clock signal and i tried, it's working...
Thanks a lot