Question about Traffic Light Controller Implementation.

[anushina]

Hi,

I have a question about implementation of my 4-state traffic light system (I have the code in VHDL). I'm using Xilinx ISE Webpack 10.1 and I got Spartan 3 XSA3S1000 starter kit board. I almost have no experience with it, only completed the tutorial so far...
My VHDL code includes the counter with reset, FSM with 4 states..where do I go from here, should I create a schematic or there's a way to implement the code directly?
Thanks
Ganna

Code below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TLC is
port(
clk,reset, sa, sb:in std_logic;
Ga, Ya, Ra, Gb, Yb, Rbut std_logic
);
end TLC;

architecture Behavioral of TLC is

type state_type is (a, b, c, d);
signal state_reg, state_next: state_type;
signal Pre_Q, Q: std_logic_vector(3 downto 0);
signal count, clear: std_logic:='0';

begin

-- behavior describe the counter
process(clk, count, clear, reset)
begin
if(reset='0') then
Pre_Q <= "0000";
Q <= "0000";
else
if (clear = '0') then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clk='1' and clk'event) then
if (count = '1') then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end if;
Q <= Pre_Q;
end process;


-- state register

process(clk,reset) begin
if(reset='0') then
state_reg <= a;
elsif (clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;

-- next state logic
process(state_reg,Q,sa,sb,reset) begin

if(reset='0') then
count <= '0';
clear <= '1';
end if;

case state_reg is
when a =>
if(sa = '1' and sb = '0')then
state_next <= a;
count <= '0';
elsif (sa = '0' and sb = '1') then
count <= '1';
if(Q = "0110") then
state_next <= b;
end if;
end if;

when b =>
if(Q = "0111") then
state_next <= c;
count <= '0';
elsif(sa = '1') then
state_next <= b;
end if;

when c =>
if(sa = '0' and sb = '1') then
state_next <= c;
elsif (sa = '1' and sb ='0') then
clear <= '0';
count <= '1';
if(Q = "0110") then
state_next <= d;
end if;
end if;

when d =>
if(Q = "0111") then
state_next <= a;
count <= '0';
elsif(sb = '1') then
state_next <= d;
end if;
end case;
end process;

process (state_reg) begin

Ga <= '1'; Ya <= '0'; Ra <= '0';
Gb <= '0'; Yb <= '0'; Rb <= '1';

case state_reg is
when a =>
when b =>
Ga <= '0';
Ya <= '1';
when c =>
Ya <= '0';
Ra <= '1';
Gb <= '1';

when d =>
Gb <= '0';
Yb <= '1';

end case;
end process;

end Behavioral;

 

[Marcel Majoor]

For an actual implementation you, at least, need to define were the signals of the entity declaration are connected to the hardware.
In your project, with the top module selected, look under 'User Constraints' and activate 'Floorplan IO - Pre-Synthesis'. This will allow you to define were your hardware is connected to (which pin of the FPGA), and what kind of logic is used (each bank of I/O's can have a different supply voltage).

If you already have a constraints file for your board (a .ucf file), then you can add this source first to your project (and optionally modify it later using 'Floorplan IO...).

Then you can use 'Implement Design' and/or 'Generate Programming File' etc.

Typically such code is first 'debugged' using a test bench and a simulator, and then actually implemented in hardware.