Question about the sub ADC stage in pipelined ADC

[arc]

Hello friends...

i am designing a 1.5bit stage pipelined ADc.

i have a question about the first stage that is sub ADC

how do i decide the threshold and Vref for both the comparator.....so i will be able to get all the combination of output.... means 00,01,10,11.. etc...

Thanks

 

[elbadry]

Re: PIPELINED ADC

Vref will depend on the maximum allowable swing of the OTA. Usually, swing = 2*Vref for differential implementation. It also determines the maximum allowable analog input level ( set to be vref peak ).

According to Vref, you set the threshold voltages.

 

[stuck_adc]

Re: PIPELINED ADC

it depends on the input swing.
in case of flash adc, consider your comparator.........the lower verf will be decided that none of the transistors should be in cutoff.........similarly higher vref is the point beyond which transistors start entering in the linear region.


you can use the large signal analysis to solve these values.

and take the appropriate values in between these 2 values.........as you are sure that the input voltage between these range will have all the transistors in saturation, fullfilling the basic requirement.....having all devices working in saturation region.




the reference range should be the same for each stage, what you need to do is to amplify the residue back to the normal range, so that our reference levels are fixed for all stages.
hope this helps.