Re: PIPELINED ADC
it depends on the input swing.
in case of flash adc, consider your comparator.........the lower verf will be decided that none of the transistors should be in cutoff.........similarly higher vref is the point beyond which transistors start entering in the linear region.
you can use the large signal analysis to solve these values.
and take the appropriate values in between these 2 values.........as you are sure that the input voltage between these range will have all the transistors in saturation, fullfilling the basic requirement.....having all devices working in saturation region.
the reference range should be the same for each stage, what you need to do is to amplify the residue back to the normal range, so that our reference levels are fixed for all stages.
hope this helps.