question about the output of the sigma delta modulator

[wqy1985]

I have a question about the out of the sigma-delta modulator. I read some references about the sigma-delta ADC. They say there need a high pass filer in the digital decimation filter in the ADC to reject the DC offset. But I don't know where the DC offset come from, and how to reject it. Is a simple IIR filter is enough? And I also want to know how to decide the specification of the high pass filter. A reference says they use a high-pass filter with a cutoff frequency of 2Hz, and another reference sats they use a high-pass fiter with a cutoff frequency of 20Hz. I am so puzzled about it and need some help.

So thanks for your response

 

[wqy1985]

waiting for the answer

 

[wqy1985]

~~~~~,somebody help

 

[drizzd]

Given a constant filter order, the greater the cutoff frequency the better the DC offset rejection, but signal distortion also increases with increasing cutoff frequency. The optimal setting depends on the amount of DC offset generated in the ADC and how much you care about error due to distortion.

 

[FvM]

You didn't tell about your application, how can we know about the requirements? I think, most SD ADCs don't use a high-pass,
because they either need to process DC or offset isn't an issue. Why do you need a filter?