question about the low power design strategy

[s8319]

as there so many low design method in ASIC design, how shoul i choose th most suitable ones, are there any document about the guidlines on the low power design strategy?

thank you !

 

[Garbielhijo]

Search for Clock domains and switching.
It can help you to inderstand some techinics to reduce the power consumption.

 

[linuxluo]

hi,
I think there is no such much methods we can choose. if you are interested in this erea, you can check cadence/synopsys/magma web and after that you can find that the methods they provide are almost the same.

 

[avimit]

You may want to have a look at my web site:
http://www.vlsiip.com/low_power.html
You may be able to find here some techniques used
But which and what to select may depend upon what you are designing.
Some of them are however general and may be applicable in majority of cases.
Kr,
Aviral Mittal

 

[eternal_nan]

Here are some of the things to look up:
1. Clock gating inserted by synthesis tool
2. Top level clock gating (inserted by designer)
3. RAM segmentation (split up large ram into several small ones, than only power the one you are using)
4. Power gating for leakage savings
5. Voltage scaling

 

[nav_vlsi]

u can also try using multi-Vt cells if your library supports it. that do give an significant improvement

 

[spauls]

You can also try MTCMOS techniques.

 

[manu_leo]

Hi,
There are many ways through which u can reduce power consumption.
If u want to reduce Dynamic power consumption use multiple voltage islands.
If u want to reduce leakage power use High Vt cells in non critical logic part and low Vt in critical ones.
MTCMOS is another good technique but it adds area overhead and leakage power remains unaltered