question about the gated clock in the multirate system

[wqy1985]

I am designing a multistage multirate system. it has 4 stages. all of them share the same main clk. the filter stage's operation frequency is clk, the second stage's operation frequency is 8 times smaller than clk. so I design a counter in the stage 1. every 8th clk period, the stage 2 get a clk_enable high level. In the 2nd and 3rd stage , there also have counter for the 3rd and fourth stage. The simulation in the modelsim is all right.
my question is that can such gated clock be used in the DC and Astro for the CTS?Or, is there any things that I have to pay attention to.
So thanks

 

[windzjy]

I think there is no problem, in our designs ,we do it in this way, the low frequency is only the enable signal , the clock is also the main clk .