Question about the differnece of ATPG simulation

[kunjalan]

atpg test_setup

Hi,
I had synthesis some logics and got a ATPG results.
ATPG tool reports 99.8% fault coverage.
And ATPG tools simulated by itself and reported no error.
But I have differnet results between ATPG simulator and NC-verilog simulator.
when I simulates with NC-verilog, next error messages are coming.
I am very compilcated by this point.

ncsim> run
// 0.00 ns : Begin test_setup
// 200.00 ns : Begin patterns, first pattern = 0
// 200.00 ns : ...begin scan load for pattern 0

// *** ERROR during capture pattern 1, T= 55300.00 ns
1 sd (exp=1, got=0)
1 row_addr[8] (exp=0, got=1)
1 row_addr[6] (exp=1, got=0)
1 row_addr[4] (exp=0, got=1)
1 row_addr[2] (exp=1, got=0)
1 row_addr[0] (exp=0, got=1)
1 hs_enb (exp=0, got=1)
1 data_enb (exp=1, got=0)
1 eoc_det (exp=1, got=0)
1 line_reset0 (exp=0, got=1)
1 line_reset2 (exp=1, got=0)
1 line_reset4 (exp=0, got=1)
1 line_reset6 (exp=1, got=0)
1 line_reset8 (exp=0, got=1)
1 line_reset10 (exp=1, got=0)
1 line_reset12 (exp=0, got=1)
1 line_reset14 (exp=1, got=0)
1 line_reset16 (exp=0, got=1)
1 line_reset18 (exp=1, got=0)
1 line_reset20 (exp=0, got=1)
1 line_reset22 (exp=1, got=0)
1 line_reset24 (exp=0, got=1)
1 line_reset26 (exp=1, got=0)
1 line_reset28 (exp=0, got=1)
1 line_reset30 (exp=1, got=0)
1 line_reset32 (exp=0, got=1)
1 line_reset34 (exp=1, got=0)
1 line_reset36 (exp=0, got=1)


who can explain this problem.

Why these reulsts are coming?

Please explain how can i overcom this problem.

Thanks

 

[cnspy]

Does anyone have the materials on the SIMULATION for ATPG?

Thanks in advance.

 

[Thomson]

Can anybody tell the major difference between ATPG and other simulation methods? and any has good books or documents for this method?


Thanks in advance!