sebas
Junior Member level 2
Hi,
A newbie's question, in the following code:
why is the writing done sequentially and the reading purely combinational? That is writing inside an always activated on the front edge of clk and reading in a continuous assignment.
Thanks
A newbie's question, in the following code:
Code:
module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)
reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
if (wr_en)
array_reg [w_addrl <= w_data;
assign r_data = array_reg [r_addr];
endmodulewhy is the writing done sequentially and the reading purely combinational? That is writing inside an always activated on the front edge of clk and reading in a continuous assignment.
Thanks