Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question about the bottom plate and parasitic capacitance in this DAC capacitor

Status
Not open for further replies.

hsinli

Newbie level 1
Joined
Jul 4, 2007
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,286
Hi all
I have two questions
1. Why the circuit is insensitive to parasitic capacitance?
2. The bottom plate of the capacitor is connecting to the opamp, is it ok?

thanks
 

hung_wai_ming@hotmail.com

Full Member level 6
Joined
Jan 5, 2004
Messages
383
Helped
52
Reputation
104
Reaction score
11
Trophy points
1,298
Activity points
2,464
About DAC capacitor

Bottom plate should be connected to VREF+/-.
As bottom plate is always connected to VREF+/-, so impedance is low, relatively compared to some floating nodes, so insensitve to noise.
Remember all floating nodes are sensitve to noise as impedance is not well defined and any charges from noise injected to that node will accumulate and cannot skip away.
Upper plate is at 1 metal layer or poly layer normally higher than the bottom plate, so intrinsically less noise sensitve, also it is at the output of the op-amp, which is also a low impedance node, so noise is insensitive
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top