Question about synthesizinggate level netlist

[ASIC_intl]

About synthesis

I have a synthesized gate level netlist. From that netlist I want to create another gate level netlist where the clock priod will have a higher time period than the earlier gate-level netlist which I have with me now. Is there any way to do that with a synthesis tool?

Thanks
ASIC

 

[VitalyM4]

Re: About synthesis

Hi, change clock period, check report_timing, if there is no slack violation with new frequency, I think you don't have to do anything.
Which tool do you use?

 

[ASIC_intl]

Re: About synthesis

Hi

DC is being used.

The gate level netlist which I have now was generated from some basic RTLs. I do not have those main RTLs now. If I synthesize with the new clock period taking this gate level netlist (which I have with me now) as the input I will face the following problem. The synthesized netlist will definitely have the newer clock period but the new netlist that I will synthesize may not be optimized in terms of GATE counts and power. I mean to meet the new timing the synthesis tool will not be able to remove the unnecessary gates which are already present in the gate level netlist which I have with me.

I would have got the best synthesized netlist with new clock period if I would have the original RTLs.

I think I am able to make u understood clearly. If not please inform me.

 

[silencer3]

About synthesis

take the netlist and do a incremental compile by giving new clock period. as this new target frequency is less than the original netlist met; target for area optimization. once u get the area optimized netlist after the incremental compile, timing check. if timing passes, then u have a design which meets the new target and with less area

 

[ASIC_intl]

Re: About synthesis

What do you mean by incremental compil here? I am not getting your point step by step

 

[shaista]

About synthesis

hello every one i want to know that how would i start studying xilinks and synthesis tool i m starting a project on verilog based design so that is why i need

 

[ASIC_intl]

Re: About synthesis

Hi
silencer3
can u please clear it out?

 

[kaustubh]

Re: About synthesis

This is my understanding from your question (correct me if i am wrong !) : you basically want a netlist that corresponds to the highest frequency possible.
Basically, its a trial and error approach..you keep giving decreasing values for the time period in your "create_clock" command and then generate a timing report..(using "report_timing" command) to check if there are any violations... the value of the time period that just generates a timing violation should correspond to your best possible frequency ...