Question about synthesizing the "Inverter Chain" b

[ckcson]

Dear All:

I have an important question about synthesize the inverter chain by using the
Synopsys Design Compiler.

I want to make a odd-number inverter chain to build a digital oscillator.
But the Design Compiler will optimize my design.
What can I do ?

I have try to use the "dont_munch" description , but it still can't fit my idea.

these are my verilog code:

module ring_osc(enable,out1,out2,out3,out4,fout);
input enable;
output fout;

output out1; //synopsys dont_munch "out1"
output out2; //synopsys dont_munch "out2"
output out3; //synopsys dont_munch "out3"
output out4; //synopsys dont_munch "out4"

nand (out1,enable,fout);
not (out2,out1);
not (out3,out2);
not (out4,out3);
not (fout,out4);

endmodule



Thanks a lot for your suggestion.

 

[dcreddy1980]

Re: Question about synthesizing the "Inverter Chain&amp

if u r question is to build up a odd number inverter chain then
try to put dont_use even number inverter cells in the synopsys setup file and the DC will use u r odd number inverters for the optimization..hope u got what i am trying to say.

and also specify "set_max_delay" ...depending up on the specified delay it will build up the inverter chain.

Regards,
dcreddy

 

[wkong_zhu]

you must use dont_touch on library cell, not math logic.
synopsys will translate math logic to GTECH library, then map to target library. If you want delay chain.
Just use target cell directly. then set_dont_touch on them.

 

[ckcson]

Re: Question about synthesizing the "Inverter Chain&amp

you must use dont_touch on library cell, not math logic.
synopsys will translate math logic to GTECH library, then map to target library. If you want delay chain.
Just use target cell directly. then set_dont_touch on them.

when I read the "inverter_chain.v" file in,it will automatically translate to G_tech library. The schematic has been optimize(already not the original schematic what I want) ,what can I do with that?

Thanks^^

Added after 2 minutes:

if u r question is to build up a odd number inverter chain then
try to put dont_use even number inverter cells in the synopsys setup file and the DC will use u r odd number inverters for the optimization..hope u got what i am trying to say.

and also specify "set_max_delay" ...depending up on the specified delay it will build up the inverter chain.

Regards,
dcreddy

Sorry,I didn't got your point.
Use the even number inverter in setup file?
Could you describe more detail?
Thanks

 

[dcreddy1980]

Re: Question about synthesizing the "Inverter Chain&amp

what i meant is...in your synopsys setup file...u can specify which of the cells from the standard cell library shouldn't be used during synthesis...

For example :

set_dont_use *IV*2
set_dont_use *IV*4

The above two commands should be present in the setup file and once they are in the setup file...u r inverter chain will not have inverters with X2 or X4 at all in the final netlist.

I hope ...u did get my point.

Regards,
dcreddy

 

[ckcson]

Maybe I have to make myself understandably.
If I try to form a inverter chain like this:
In---inverter---out1---inverter---out2---inverter---out3----inverter---out4----inverter---out
When I read the verilog file in the DC,the schematic view will be translated to this (with G_tech)
**broken link removed**

Thanks for your helping.
I'm very appreciated

 

[dcreddy1980]

Re: Question about synthesizing the "Inverter Chain&amp

Did u get what u want?

or Still u have doubhts regarding the approach?

Regards,
dcreddy1980

 

[quenstin]

Dear All:

I have an important question about synthesize the inverter chain by using the
Synopsys Design Compiler.

I want to make a odd-number inverter chain to build a digital oscillator.
But the Design Compiler will optimize my design.
What can I do ?

I have try to use the "dont_munch" description , but it still can't fit my idea.

these are my verilog code:

module ring_osc(enable,out1,out2,out3,out4,fout);
input enable;
output fout;

output out1; //synopsys dont_munch "out1"
output out2; //synopsys dont_munch "out2"
output out3; //synopsys dont_munch "out3"
output out4; //synopsys dont_munch "out4"

nand (out1,enable,fout);
not (out2,out1);
not (out3,out2);
not (out4,out3);
not (fout,out4);

endmodule



Thanks a lot for your suggestion.

U can separate it as a cell and set_dont_touch, then it will not be optimized