Question about stages disturbance of Pipelined ADC

[w98211012]

I have taken part in a project of Pipelined ADC about two months. The design of all sub-blocks has finished, and the simulation results of these sub-blocks meet our requirements. But when we put all stages together, the simultion curves showed the signal got great attenuation. We designed a high speed buffer to settle the troubles what we came acrossed, the situation got better, but the problem still wasn't settle completely. Is there anybody can give me some advice?

 

[safwatonline]

i don't know about ADCs that much but u check the switches

 

[w98211012]

i don't know about ADCs that much but u check the switches

safwatonline,
Thank u for your advice, but the problem was not caused by the switches.