question about slices

[kannan2590]

The question is how to use dsp 48 slices in vhdl code.I am using virtex 4 fpga.Is dsp 48 an ip core in xilinx software

 

[TrickyDicky]

usually

a <= b * c;

does the trick.

 

[kannan2590]

usually

a <= b * c;

does the trick.

Is "*" a DSP 48 slice?

 

[TrickyDicky]

* is a multiply in VHDL. It should infer a DSP slice when synthesised.

 

[kannan2590]

* is a multiply in VHDL. It should infer a DSP slice when synthesised.

Is there any other method other than "*" to make use of dsp 48 slice in vhdl?

 

[TrickyDicky]

you could instantiate a multiplier block, or directly instantiate a DSP48 block primitive.

 

[kannan2590]

you could instantiate a multiplier block, or directly instantiate a DSP48 block primitive.

How to instantiate a multiplier block or directly instantiate a DSP48 block primitive?Can you explain it to me?

 

[TrickyDicky]

Use the unisim library. What kind of detail are you after? can you tell use why you want to do this and not just infer a multiplier like I origionally said you could do?

If you are looking for VHDL help, I suggest you read a VHDL tutorial, specially on instantiating an entity.

 

[kannan2590]

Use the unisim library. What kind of detail are you after? can you tell use why you want to do this and not just infer a multiplier like I origionally said you could do?

If you are looking for VHDL help, I suggest you read a VHDL tutorial, specially on instantiating an entity.

i tried to use ip core for multiplier but still it is not sitting on dsp 48 slices

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity mult8 is
port ( a:in std_logic_vector(17 downto 0);
b: in std_logic_vector(17 downto 0);
clk:in std_logic;
c: out std_logic_vector(35 downto 0)
);
end mult8;

architecture Behavioral of mult8 is

component multiplier1
port(clk:in std_logic;
A:in std_logic_vector(17 downto 0);
B:in std_logic_vector(17 downto 0);
Put std_logic_vector(35 downto 0)
);
end component;

begin



insmultiplier:multiplier1 port map(
clk => clk,
A =>a,
B =>b,
P =>c
);


end Behavioral;

can you tell me the reason?

 

[TrickyDicky]

Without the full code for reference - no idea.
Have ytou connected all inputs? do you get any warnings during synthesis about logic begin removed? Are the inputs constant?