question about sigma delta ADC

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sapphire

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Hi, my question is about the synchronization between signal delta modulator and decimation filter.

The data coming out of the modulator is going to be clocked into the decimation filter. Due to some propagation delay and some interconnect delay, how can the digital clock sample at the middle of each bit duration? What I thought is we can use some kind of DLL? But I am not clear about how to implement it?

Please teach me how to do it or correct me if I am wrong. Thank you very much.

Edward
 

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