Question about RS Flip Flop for PWM Control system?

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Y.C Park

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pwm rs flip flop

HI Expert!!!

I am an Ananlog Design Engineer.
So I am very weak for Digital Design.

Is it possible to design Clockless Edge Triggered RS Flip Flop?
Now I have to design a PWM Power IC.
But I have no idea about Edge-Triggered Set Reset Flip Flop without clock.

Could anyone show me the method?

Attached schematic is an example.
But it has a malfunction when a set signal triggerd high on RESET is high state.

Thanks in advance.
 

you can design SR FF without clock at all BUT the SR FF suffers from some problem
i suggest for u to try the JK FF
for more info i suggest u to read in book like the book of Mano ( digital Design)
 

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