question about power plan about memory

[lightcloud]

Hi,

I do power plan of the chip,but I dont know the scheme of my plan is
reasonbale. can someone supply some suggestion

the power of my chip is 500mw, my power plan scheme as followed:

metal6 width:10 picth:50 space:100
metal5 width: 5 picth:25 space:50
metal4 width:4 picth:50 space:100

strap of metal5 and metal4 mainly supply the connection of memory and power
rail of standard cell.

I have a question, as to avoid pin of memory, I connect memory using metal4/
metal5 to connect only side which have no pins, does it affect IR drop of memory
or how to connect ring of the memory


best regards

 

[hiral.kotak]

Hi,

Pls visit the site : https://asic-soc.blogspot.com/2007/10/power-planning.html
It may help you.

Thanks..

HAK..

 

[lightcloud]

thanks a lot! I will look at it