Question about pole and zero of LDO

[wwwww12345]

Help!

I designed a new LDO base upon Rincon-Mora 's paper, but no bypass capacitor (Cb). What is strange is that my seconde pole(in the gate of the pass transistor) is always lower than the first zero(made by the ESR and external capacitor ). And my ac simulation is right, showing the phase margin is above 60 degree. I saw a lot of other paper, all saying the second pole lower than the firest zero. Am I wrong??? Do any one have the same result of mine?

 

[caosl]

Re: Pole and zero of LDO

you can do the simulation after changing some parameters such as output cap and its' esr, the Power mos's dimension, the second pole is not necessary larger or smaller than the pole created by output cap and its' esr.

 

[wwwww12345]

Pole and zero of LDO

Thank you. Your help is very appreciated !