Question about PLL synthesizer

[liberal]

pll synthesizer definition

I designed a 800MHz PLL synthesizer,VCO is MQE001-800.But the freuency is not stable,and Changes around 800MHz quickly.Which Part shoul i consider and check?and how?

 

[xtasa]

HI :roll: :idea: Liberal,

Your design is not good . If you have frequency which you want and voltage is in possible range (for example with power supply VCC 5V control voltage inside PLL loop is between 0.5-4.5V) PLL loop is not designed good. Check your data for PLL design or wide or limit loop bandwith.

GL XTASA

 

[biff44]

Any phase locked loop that has a loop filter that is an integrator is, by fundamental theory, most likely to be unstable. That is because the integrator provides 90 degrees of phase shift and the oscillator provides another 90 degrees of phase shift, resulting in a control loop with zero or worse phase margin (can be worse than 180 if there are extra bypass capacitors to ground, time delay, etc). A control loop with 0 degrees of phase shift is, by definition, an oscillator!

Smart PLL engineers anticipate this, and design a "zero" into the loop filter so that when the open loop gain crosses 0 dB, the open loop phase shift is at least 45 degrees short of 180.

Assuming something is not broken, you are trying to lock your vco within its possible tuning range with correct divisor ratios, and you have the loop polarity right, odds are that you have no phase margin and need to move your "zero" lower in frequency.

Simply lowering the bandwidth does not necessarily mean the loop will suddenly become stable, you might just end up with a 1 Hz oscillator!

 

[rf100]

hi
Try to add a small capacitor as near as the tuning pin of your vco this capacitor may increase the lock time but should make your spectrum more clean
and lock your signal
Best wishes

the value of the capacitor can be between 1 nF to 1 uF

 

[liberal]

To rf100
:
the capacitor is serial or shunt?

 

[wangjianhui]

maybe shunt I think

 

[rf100]

yes it is in shunt

 

[liberal]

still bad.the lock voltage is 5V.when i close the loop,the Vtune is unstable ,changes below 5V.
Can u give me some experience to deal with it?

 

[biff44]

Yeah, its broken...that is my general comment.

If you want specific advice, you might give us your VCO tuning constant, phase detector gain constant, details of the loop filter design, EVERYTHING that you have tried so far (have you tried to change tuning polarity, for instnace) etc.

 

[liberal]

In fact,This Pll is a component in a SA.Then i think all the correlative parameters are well.so why?

 

[liberal]

done.
The mixer as a PD is bad.

 

[spikeyang]

Nowadays, the only components you can adjust is the loop bandwidth. When the IC is bad,What a tradgedy.Hmm...

 

[eecly]

Hi,

Have u checked whether the frequency is locked? If u find it is not stable. The frequency may be be lcoked.

There are many reason why the PLL is unlock. First, loop filter design it critcial . Improper loop filter design may cause the PLL unlock. You can use ADIpll SIM like software to design your own loop filter. You can enter various parameter like VCO gain, loop BW, charge pump current....etc into the software. You can obtain the loop filter circuit from simulation software.

Pls also check your reference (xtal maybe). Is it stable enough? If the ref. is unstable, the output frequency is also unstable.

eecly

 

[vagarwal]

after so much discussion, there is nothing much left... only possibilites that occur to me are either a redesign with proper calculations and constants or maybe a manual tuning of loop filter components.

Are you using an active loop filter??

Reference also can be checked for stability.