Any phase locked loop that has a loop filter that is an integrator is, by fundamental theory, most likely to be unstable. That is because the integrator provides 90 degrees of phase shift and the oscillator provides another 90 degrees of phase shift, resulting in a control loop with zero or worse phase margin (can be worse than 180 if there are extra bypass capacitors to ground, time delay, etc). A control loop with 0 degrees of phase shift is, by definition, an oscillator!
Smart PLL engineers anticipate this, and design a "zero" into the loop filter so that when the open loop gain crosses 0 dB, the open loop phase shift is at least 45 degrees short of 180.
Assuming something is not broken, you are trying to lock your vco within its possible tuning range with correct divisor ratios, and you have the loop polarity right, odds are that you have no phase margin and need to move your "zero" lower in frequency.
Simply lowering the bandwidth does not necessarily mean the loop will suddenly become stable, you might just end up with a 1 Hz oscillator!