haadi20
Full Member level 1

Referring to Keliu Shu book on CMOS PLL synthesizers, Eq. Nr. 3.7 gives the PLL loop gain as K= (Kpd Kvco R1) / N
where Kpd is the PFD gain
Kvco is the VCO gain
R1 is part of the 2nd order loop filter
and N is the divide ratio
My question is which value of N should be used in this equation, because N has a range for an Integer N PLL and its not constant ?
Looking forward for replies...
where Kpd is the PFD gain
Kvco is the VCO gain
R1 is part of the 2nd order loop filter
and N is the divide ratio
My question is which value of N should be used in this equation, because N has a range for an Integer N PLL and its not constant ?
Looking forward for replies...