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Question about PLL design equation

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haadi20

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Referring to Keliu Shu book on CMOS PLL synthesizers, Eq. Nr. 3.7 gives the PLL loop gain as K= (Kpd Kvco R1) / N
where Kpd is the PFD gain
Kvco is the VCO gain
R1 is part of the 2nd order loop filter
and N is the divide ratio

My question is which value of N should be used in this equation, because N has a range for an Integer N PLL and its not constant ?

Looking forward for replies...
 

khouly

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some times , it the geometrical mean , of the max and min , valuse of N

or the normal mean , try both

khouly
 

dinesh agarwal

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it is max devider ratio ssuppose reference freq is 5 M hz and the vco output freq is 1G hz than N=200.

think clear if not reply again
 

rania_hassan

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Hi,
N is the geometric mean as Kholy said
khouly said:
some times , it the geometrical mean , of the max and min , valuse of N

or the normal mean , try both

khouly
 

VSWR

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The loop gain is NOT constant, it varies proportional to 1/N over your range of N values. It is important to analyze what impact varying K will have on the loop stability (amplitude margin and phase margin). In many cases Kvco varies as well with tuning voltage and you have to take this into account as well.

haadi20 said:
Referring to Keliu Shu book on CMOS PLL synthesizers, Eq. Nr. 3.7 gives the PLL loop gain as K= (Kpd Kvco R1) / N
where Kpd is the PFD gain
Kvco is the VCO gain
R1 is part of the 2nd order loop filter
and N is the divide ratio

My question is which value of N should be used in this equation, because N has a range for an Integer N PLL and its not constant ?

Looking forward for replies...
 

    haadi20

    points: 2
    Helpful Answer Positive Rating
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