ruwan2
Member level 5
Hi,
When I read a tutorial on FIR implementation on FPGA, I am not clear about
With the below picture, could you tell me how to understand about the partial results?
Thank,
When I read a tutorial on FIR implementation on FPGA, I am not clear about
That slide may be based on multiplier with logic cell in FPGA, not a dedicated MAC in FPGA. Anyhow, I don't know why 'partial results can be used for many multiplications (regardless of symmetry)'? I only think that to save 50% multiplier taking advantage of FIR coef symmetric characteristic."partial results can be used for many multiplications (regardless of symmetry)"
With the below picture, could you tell me how to understand about the partial results?
Thank,