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Question about partial multiplication result in transposed FIR filter

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ruwan2

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Hi,

When I read a tutorial on FIR implementation on FPGA, I am not clear about
"partial results can be used for many multiplications (regardless of symmetry)"
That slide may be based on multiplier with logic cell in FPGA, not a dedicated MAC in FPGA. Anyhow, I don't know why 'partial results can be used for many multiplications (regardless of symmetry)'? I only think that to save 50% multiplier taking advantage of FIR coef symmetric characteristic.
With the below picture, could you tell me how to understand about the partial results?

Thank,

partialM.PNG
 

I don't understand either. Depends on the rest of the article maybe?
One thing that comes to mind is you may be able to build some form of table from the results for future and inter reference.
But that's the kind of complex my frontal cortex is trying to meddle with the proces..
Any way shape or form would not be my cup of thee, I'd go for brute force.
 

Possibly refering to the fact that as the Din value is the same, if there is comonality between coefficients (ie, the 4lsbs are the same) you can just use 1 multiplier for that half of the word and replicate the data twice (as a multiply is just a sum of bitshifts).

Either way, I guess this paper is rather old - Id be very surprised to see anyone using logic multipliers in modern FPGAs.
 
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