question about mosfet

[ilikebbs]

Now i want to use N-MOSFET to realize data isolation.
G is connected to 3.3v
S is connected to 3.3v data bus.
D is connected to 5v data bus.
Does the circuit can work?
I think that it can work.
Do you agree with me?

 

[max0412]

No .The gate of an N-channel mosfet must be pulled above the source by at least the threshold voltage.

So for example say your using a logic level mosfet you would have to apply about 8V to fully turn it on, if your source is at in this case 3.3V.

 

[ilikebbs]

the 3.3v data bus is pulled up to 3.3v
the 5v data bus is pulled up to 5v
Does it can realize the level shift?
From the direction of 3.3v data to 5v data, it is no problem.
But from the direction of 5v data to 3.3v data, Does it work?

 

[max0412]

No you must have at least the minimum data sheet (Vth) plus a margin for component tolerances and for thermal adjustment. In your case your Vgs would only be about 1.7V (5V-3.3V=1.7V) ttl FETS that I've looked at typically have Vth > 2V. You also have a small Vds, I don't know what your desired Ids is?

I didn't see your application was for isolation, have you considered optical isolation.I don't understand how your using a mosfet for isolation? You can use it for current limiting by controlling the gate signal. This would require some additional components (complexity).

If you are determined to drive the Fet you can look into "doublers" "charge pumps" and "bootstrapping". Personally this sounds more like a job for an opto-coupler.

 

[ilikebbs]

the circuit was used for I2c level shift.
One side is 3.3V lever. The other side is 5V level.
The clock is unidirectional. It is ok.
The data is bidirectional. Someone told me that the MOSFET usage listed above can be used for level shift.
Data from 3.3V to 5V side is also Ok.
But the data from 5V to 3.3V side may have problem. The circuit works well. I do not know why?

 

[max0412]

From your original post you say :

G is connected to 3.3v
S is connected to 3.3v data bus.


Having now a better understanding of what your doing when your shifting from 5V to 3.3V your source will be at 3.3V your gate signal is 3.3V (Vg - Vs = Vgs) this would be 3.3Vg- 3.3Vs = 0Vgs this cant work (if I'm understanding you correctly).

Posting the schematic would help.

 

[nguyennam]

For S and D, it is OK since the S must be more negative than D.
But G must be more positive than S, and the delta must be the threshhold voltage at least.

nguyennam

 

[maharshi_qis]

I think ckt u mentioned may not work...whatever the voltage u appied to S&D ....G should be at excess by atleast 1Vt than S..

 

[dkace]

Let's go to basic equations:
In strong inversion saturation ( where this n-MOS operates as part of digital circuitry)

Id=k/2 *(Vgs-Vt)².

If Vgs = 0 then Id is minimized on leackage current. Not good, therefore not working.

See it from another point of view. If the two voltages are identical and Vgs=0, then there is no depletion region below S and now inversion layer on the surface of the Gate. The n-MOST can't wotk because there are no carriers to do the job, no channel to go through.

What do you think now?

D.

 

[iggyboy]

No, it will not work. First you should ensure a "referense" point on the S. You can use a pull-down to reference s to ground and your circuit will work to within 1V or so bellow 3.3V, which amounts to around 2.3V peak. Actually alittle more, since a lower Vgate-source voltage is needed for lower currents. Sadly this won't help, as most mcu won't interpret voltages below 2,7V as a logical "1".

 

[10kangstroms]

I think that the source is connected to a bus that swings between 0V and 3.3V. The drain is connected to a bus that swings 0V to 5V. The gate is connected to 3.3V. I believe there are mosfets with guaranteed Rds at Vgs=3.3V, so this basically acts like a common gate amplifier, only in the digital domain. So long as the 5V bus pullup impedance is high relative to the 3.3V bus pulldown impedance, it should work.

 

[iggyboy]

But the data from 5V to 3.3V side may have problem. The circuit works well. I do not know why?

I think I understand now. For data transmission from 3.3V towards 5V, G is at 3.3V as you said, and by wiggling G, you control directly the conductance of the transistor. However from the 5V towards 3.3V, you really do not control anything. If a line at the 3.3V is pulled low (S is at 0V), the mos is on. If under these circumstances the D is low, the whole bus is low and if D is high, the whole bus is high (well not really, betwen 3.3 and 2.0V) That is, if the mos is on, everyhing will be ok. But what if the mos is off (S is high for some reason)? Wiggling the D about won't help much, as the transistor is shut-off anyway. So the danger lies when S is kept high when this should not be so. Maybe because of capacitance or similar efect and after D goes low, the mos won't be switched on until the S falls low enough. Maybe your circuit works because pulldowns between sources and 0V?

I would suggest about 4V at the gates and pull downs at the 3.3V bus. Or even better. If it aint broken, don't fix it