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Question about low frequency SDRAM controller design

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boku

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About SDRAM's CLK

Hello, I'd like to design the sdram controller. After surveying the current SDRAM frequency, the most common is 100/133MHz. What if my design doesn't run in such high freqency. It's only 60 MHz or 30 Mhz in my design. So can I just use low clock freq into SDRAM module's CLK???
Thank you so much!~~~ :roll:
 

Yes it can run at any frequency. I have designed SDRAM controller that runs at 33 MHz and there is no problem. Just make sure you refresh your RAM.


ASIC
 

Thank you very much. You mentioned about the refresh issue. If the sdram I use is 64ms, 8192-cycles refresh time and my clock freq is 30 MHz, does it mean that the sdram controller needs to refresh every (64,000,000/8,192)ns/(1000/30)ns=234 cycles averagely??
ASIC said:
Yes it can run at any frequency. I have designed SDRAM controller that runs at 33 MHz and there is no problem. Just make sure you refresh your RAM.


ASIC
 

Yes. You can issue the auto-refresh command on average 234cycle. At 30MHz, no idle cycle is needed for the precharge (Most SDRAM require ~20ns only) You can also use CL=2. Both can help maximizing the through-put data rate.

Good reference design can be found below: (GPL License)
**broken link removed**

boku said:
Thank you very much. You mentioned about the refresh issue. If the sdram I use is 64ms, 8192-cycles refresh time and my clock freq is 30 MHz, does it mean that the sdram controller needs to refresh every (64,000,000/8,192)ns/(1000/30)ns=234 cycles averagely??
ASIC said:
Yes it can run at any frequency. I have designed SDRAM controller that runs at 33 MHz and there is no problem. Just make sure you refresh your RAM.


ASIC
 

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