Question about ldo stability, need your help!

[colinwang]

stability with a margin

Hello everyone,
I've designed a traditional ldo. And I added the parasitic resistors and inductors of the bound wire and pad. The values of them is around 200mOhm and 1nH. The ac simulation shows the loop is stalbe and I also performed the stb analysis under several load conditions and the phase margins are all above 70deg. But when I did the transient simulation of the circuit, the problem happened. After the circuit started up, i changed the load current and the output began to oscillation. The oscillation frequency is around 8MHz and it's regular. The loop gain bandwidth is around several kHz. I use the conservative accuracy with 10ns maxstep. If I change the maxstep to 20ns, the oscillation disappeared. I know the smaller the step is, the more accurate the result will be.
But why the loop analysis shows the circuit is stable but finds oscillation the transient simulation? Is that to say the phase margin is necessary but not sufficinet to the stability? Or there are some other reasons? Need your help!
I did the ac simulation using a huge inductor in the feedback loop and a huge capacitor to couple the ac signal to the positive node of the op. and I did the stb analysis by putting an ac source in the feedback loop.
The transient simulation is that after the ldo started up, the load current changed 20mA in 1us.
Need your help!


Regards,
Colin

 

[ricklin]

Transient analysis may deviate from ac analysis, as transient analysis may run into large signal cases which is not covered by ac.

However, this case may be an algorithm problem but not a real oscillation.

 

[colinwang]

Thank you very much.
How to ensure stability under large signal transient?
I use gear method. Which method should I use?

Regards,
Colin

 

[ricklin]

Thank you very much.
How to ensure stability under large signal transient?
I use gear method. Which method should I use?

Regards,
Colin

I think it's hard to give a rule for large signal stability, i.e.fast switching action will make circuits far from designed operating points.

Both gear or rectangular is ok, and the 1st that should be make sure is if it's an algorithm problem. You can use different simulator such as spice vs. spectre, or change simulation resolution to see if the oscillation will disappear or show difference.

 

[LvW]

Hello everyone,
I've designed a traditional ldo. And I added the parasitic resistors and inductors of the bound wire and pad. The values of them is around 200mOhm and 1nH. The ac simulation shows the loop is stalbe and I also performed the stb analysis under several load conditions and the phase margins are all above 70deg. But when I did the transient simulation of the circuit, the problem happened. After the circuit started up, i changed the load current and the output began to oscillation. The oscillation frequency is around 8MHz and it's regular. The loop gain bandwidth is around several kHz

1.) For ac simulation the use of a large inductor/capacitor is a rather crude method, however, it cannot be reason for your problems. (By te way, simply to introduce an ac source between opamp output and MOSFET input is a better method).
2.) You have analyzed the main loop (bandwidth some kHz) and it indicates stability with a margin which is sufficient. I think this is confirmed by TRAN analysis, since the oscillation is not in the kHz but in the MHz region.
3.) Therefore, I think the reason of MHz oscillations is in a hidden local loop, perhaps caused by some elements introduced by you to model parasitics.
4.) Recommendation: Remove all parasitic elements and simulate again. Perhaps also TRAN analysis is stable - and you know the cause of instabilty.

 

[colinwang]

Thank you all very much!
Truely if I removed the parasitic inductors and resistors, the oscillation disappeared. But I only add one 1nH inductor and one 0.2Ohm resistor in the input of the supply voltage and the ldo output node. Where could the other loop possible be? Thanks!

Regards,
Colin

 

[LvW]

But I only add one 1nH inductor and one 0.2Ohm resistor in the input of the supply voltage and the ldo output node.

Please, be more specific. 1 nH between which nodes ?

 

[colinwang]

ideal voltage source --> 1nH inductor --> 0.2Ohm resistor --> VDD of the circuit

 

[LvW]

1.)In your last reply at 2:42 you have mentioned that one of the parasitic elements was connected to the LDO output node.
2.) Which source supplies the opamp ? This could create a hidden loop. Try with/without parasitics.

 

[colinwang]

LDO_Output --> 0.2Ohm resistor --> 1nH inductor --> Real Output
I just use them to model the pad and bounding wire parasitic briefly.

The whole circuit uses the same power supply including the opamp: ideal voltage source --> inductor --> resistor --> circuit

If I remove the parasitc, the oscillation disappears.

Thank you!

 

[walker5678]

try to make sure the DC operatiing point you set when you run AC analysis is the same as that in the transient analysis.

 

[colinwang]

Yes, the DC operating point is right.
What makes me confused is that without the parasitic devices, the circuit works very well. Even if i add a 1.5nH inductor to the power line, the output starts to oscillate. I use conservative accuracy with 1ns maxstep. If I set 10ns maxstep, the oscillation won't be seen.
Usually the smaller the step is, the more accurate the result will be. But how small is acceptable? Is there anything related to the simulator?
Really confused.
Any reply is appreciated.

Regards,
Colin

 

[LvW]

What makes me confused is that without the parasitic devices, the circuit works very well. ....... Is there anything related to the simulator?

I don´t think that´s a simulator problem.
As the opamp is supplied via a power line which includes parasitics, try the following:
Connect a capacitor of app. 100 nF between opamp power input pin and ground (power supply bypassing). By the way, what´s the amplitude of the 8 MHz oscillation ?

 

[colinwang]

The oscillation is less than 10mV.