Question about ldo stability, need your help!

[colinwang]

Hello everyone,
I've designed a traditional ldo. And I added the parasitic resistors and inductors of the bound wire and pad. The values of them is around 200mOhm and 1nH. The ac simulation shows the loop is stalbe and I also performed the stb analysis under several load conditions and the phase margin and gain margin are also satisfied. But when I did the transient simulation of the circuit, the problem happened. After the circuit started up, i changed the load current and the output began to oscillation. I use the conservative accuracy with 10ns maxstep. If I change the maxstep to 20ns, the oscillation disappeared. I know the smaller the step is, the more accurate the result will be.
But why the loop analysis shows the circuit is stable but finds oscillation the transient simulation? Is that to say the phase margin is necessary but not sufficinet to the stability? Or there are some other reasons? Need your help!
I did the ac simulation using a huge inductor in the feedback loop and a huge capacitor to couple the ac signal to the positive node of the op. and I did the stb analysis by putting an ac source in the feedback loop.
The transient simulation is that after the ldo started up, the load current changed 20mA in 1us.
Need your help!


Regards,
Colin

 

[Medini]

Hello Colin,

A good phase margin will be 52d. Put Fc far above oscillation frequency so the loop will dump it. If oscillation frequency is above you may have simulation problem.

 

[ashish_chauhan]

Hi Collin

As you said the "oscillations" started after load change... have u chaecked the stability for different loads... ? if yes then...

Were the oscillations of somewhat irregular shape ... if so then they can be numerical oscillations also... that is a simulator problem(u said they go away when time step is a bit relaxed)

for this set method = gear in simulation options this will help you

 

[colinwang]

Thank you all
I've checked the phase margin at different load conditions and they are all above 70degree.
The oscillation frequency is around 8MHz and it's regular. The loop gain bandwidth is around several kHz.
If i don't add the parasitic resistors and inductors, it won't oscillate any more. But with them the phase margin is still above 70deg.
Enough phase margin but oscillation during load transient make me confused. It is not like this in the former design.
Any reply is appreciated.

Regards,
Colin


I use the gear method, it also oscillates.

 

[quaternion]

please make a parametric sweep (for sufficient no of points >20 ) for load current & monitor the phase margin.

 

[hung_wai_ming@hotmail.com]

Collinwang,

You put ac source in the -ve input of error amp to do AC analysis, right? and you monitor the vfb point (where the middle point of two resistors) as the output, right?

What about showed us the Bode plot to see?

 

[colinwang]

Yes, you are right.
I put a ac source(dc=0) between Vfb(in the middle of the feedback resitors) and negative input of the op. And I run the stb analysis to see the phase margin.

What makes me confused is that without the parasitic devices, the circuit works very well. Even if i add a 1.5nH inductor to the power line, the output starts to oscillate. I use conservative accuracy with 1ns maxstep. If I set 10ns maxstep, the oscillation won't be seen.
Usually the smaller the step is, the more accurate the result will be. But how small is acceptable? Is there anything related to the simulator?

 

[hung_wai_ming@hotmail.com]

Collinwang,

I don't think your AC simulation setup is correct.

What we need to do is to break the loop in vfb point and insert ac source at vref point with DC bias (vref=1.25 if you used badngap, not DC=0v) and observe the Av=Vfb/Vref, and you insert a large RC or LC to DC bias the +ve input of EA, so I think you'd better check carefully your AC setup first

 

[colinwang]

Yes, I use two ways to measure ac response. Both are got from this website.
The other way is I put a huge inductor between Vfb and positive input of op and use a huge capacitor to couple the ac signal to the positive input of op. I'm sorry that i've made a mistake in the former reply. positive node not negative node.