question about ISE 6.3 and Modelsim 6.0a

[juan_manuell]

modelsim custom editor

Hi,
I begun to work with ise 6.3 and modelsim 6.0a. My problem is that every time i launch simulation i need to close the last open modelsim sesion. If not modelsim say that there isn´t a license to work in that mode and close.

There are some script or in modelsim a command to reload the new files and do simulation without close it every time.
My machine is a little slower and take a lot of time load modelsim every time.

thanks so much for you help

 

[tlp71@hotmail.com]

modelsim fdisplay

you must simply use the upper arrow in the command line to recall the right fdo file.
You can also use a personal fdo file and lunck this as
do <namefile>.fdo

 

[echo47]

modelsim 6.0a

I use ModelSim SE 6.0c. I created a custom button that runs a tricky 'do' file that clears out the current simulation, recompiles the HDL, and restarts the simulation.

Now, using my favorite text editor, I edit my HDL and save it to a file, then click my custom ModelSim button to compile/simulate it. I can edit-save-simulate, edit-save-simulate, ... every five seconds if I want to. It's a joy to use.

 

[juan_manuell]

time en modelsim

I think that i need to read a little more about commands on ModelSim.

tlp71@hotmail.com i will try it, it appear more what i was looking for.

echo47 it is an interesting option i will do a little research about it.

In the group were i am begun to work on this, they try to work directly on modelim, edit and simulate.
I don´t like to much the idea because on ISE we have many help and utilities that made more easy our work, i don´t know if modelsim it have.
I think that modelsim it is only for simulation.

Any advise abut this ?

thanks

 

[echo47]

modelsim executing batch files from verilog

I think ModelSim PE and SE are only simulators. However, ModelSim Designer (I've never used it) contains ModelSim PE and additional stuff for building Xilinx projects. It's more than just a simulator.

I don't know if you will be able to figure out the following stuff. When I start a new project, I simply copy these three files into a new folder and type 'go'. Some parts will only work with ModelSim SE.

Here is my 'go.bat' batch file that I use to launch ModelSim:

@echo off
if exist work rmdir /q /s work
vlib work
modelsim -do go.do

Here is my tricky 'go.do' file:

if {$argc==0} {
  add button " Reload "     {do go.do -reload}      NoDisable {-bg #D0E0F0 -relief solid}
  add button " Reload Opt " {do go.do -reload-vopt} NoDisable {-bg #D0F0E0 -relief solid}
  add button " Unload "     {do go.do -unload}      NoDisable {-bg #F0E0D0 -relief solid}
}
if {$argc && $1=="-unload"} {
  onerror {resume}
  view wave
  delete wave *
  quit -sim
} else {
  onerror {resume}
  view wave
  delete wave *
  .main clear
  if {$argc && $1=="-reload-vopt"} {
    vlog -vopt -nologo $env(XILINX)/verilog/src/glbl.v *.v
    vopt +nowarnTFMPC +acc=rn+test test -o test_opt
    vsim +nowarnTFMPC -t ps work.test_opt
  } else {
    vlog -nologo $env(XILINX)/verilog/src/glbl.v *.v
    vsim +nowarnTFMPC -t ps -L unisims_ver -L xilinxcorelib_ver work.test
  }
  restart -force -noassertions -nobreakpoint -nolist -nolog -nowave
  configure wave -snapdistance 0
  log -r /*
  # The test bench initial code creates this temporary 'do' file
  run 0
  do temp.do
}

Here is a sample Verilog file that contains a simple counter and a simple test bench that also does some tricky ModelSim initialization and sets a few personal preferences:

// synthesis translate_off
`timescale 1 ns / 1 ps
module test ();
  parameter                     period = 12.5;
  reg                           clk = 0;
  integer fout, runtime;

  glbl glbl ();                 // glbl stuff needed by some Xilinx parts
  assign glbl.GTS = 1'b0;

  initial begin
    runtime = period * 50;
    fout = $fopen("temp.do", "w");
    $fdisplay(fout, "set PrefWave(gridPeriod) %fns", period);
    $fdisplay(fout, "add wave -divider top");
    $fdisplay(fout, "add wave -format Logic -radix unsigned top/\*");
    $fdisplay(fout, "run %0dns", runtime);
    $fdisplay(fout, "WaveRestoreZoom 0ns [expr 1.01 * %0d]ns", runtime);
    $fclose(fout);
    fork
      begin #(period) forever begin clk=1; #(0.5*period); clk=0; #(0.5*period); end end
    join
  end

  top top (.clk(clk));
endmodule
// synthesis translate_on

module top (clk, odata);
  parameter                     obits = 4;
  input                         clk;  // synthesis attribute period "12.5ns";
  output reg        [obits-1:0] odata = 0;

  always @ (posedge clk) begin
    odata <= odata + 1;
  end
endmodule

 

[cawan]

nowarntfmpc

You can play some tricks in .fdo file to meet your requirements. However, for complicated design as well as details verification process, it is not recommended to use the testbench generator provided by ISE. It is not sufficient to generate a really comprehensive testbench to simulate all the possible events of your digital system. It is more recommended to design your own testbench for better bugs discovery and performance observation.

 

[echo47]

modelsim 6.3 tcl

What is an 'fdo' file? I can't find that word in the ModelSim docs.

 

[juan_manuell]

modelsim waverestorezoom

I think ModelSim PE and SE are only simulators. However, ModelSim Designer (I've never used it) contains ModelSim PE and additional stuff for building Xilinx projects. It's more than just a simulator.

I was looking for some info and found that M3nt0r have a L3on@rdo Esp3ctrum to edit and work with VHDL and they have other tool more complete called @dvant@age FPGA that have a lot of tools. But definily ModelS1m it is not to work directly with proyects of vhdl.

I don't know if you will be able to figure out the following stuff. When I start a new project, I simply copy these three files into a new folder and type 'go'. Some parts will only work with ModelSim SE.

I will try it

Added after 9 minutes:

You can play some tricks in .fdo file to meet your requirements. However, for complicated design as well as details verification process, it is not recommended to use the testbench generator provided by ISE. It is not sufficient to generate a really comprehensive testbench to simulate all the possible events of your digital system. It is more recommended to design your own testbench for better bugs discovery and performance observation.

Thanks, I use only the generator to just build the body. I write my own testbench in vhdl to test all. I like ISE wizard and help because i just copy and paste, modify and compile If i need to write for the beginning a enttity or anything else i don´t know how to do it. I just begun with this languaje this is why i like ise

Added after 3 hours 18 minutes:

What is an 'fdo' file? I can't find that word in the ModelSim docs.

It is a file generated by ISE this is the file from an example that i have

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Apr 16 12:40:37 Hora est. de Sudamérica E. 2005
##
vlib work
vcom -93 -explicit  mux.vhd
vcom -93 -explicit  mux_tbv.vhd
vsim -t 1ps   -lib work mux_mux_tbv_vhd_tb
do mux_mux_tbv_vhd_tb.udo
view wave
add wave *
view structure
view signals
run 1000ns

 

[echo47]

modelsim se 6+system requirement

That 'fdo' file looks just like a ModelSim 'do' file but with a different name. Sounds like ISE's Project Navigator generates it to run ModelSim. I've never seen that file because I run ISE from a makefile instead of Project Navigator. My project requires manoeuvres that Project Navigator can't do.