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question about gclk and program the fpga through jtag

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matin-kh

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Hi everyone
I have three question:
1- when I want to program the fpga(spartan 6) doesn't need to enter an external clock to fpga?I mean jtag will enter the clock to fpga and we don't have any external clock am I right? and does need to change the mode pins of FPGA to the slave mode?
2-if I want to use the fpga as a master and enter clock to other devices from fpga does it make any difference which pin is used as output?GCLK or IO pins? if it is make difference could you please tell me why?
3-I want to know more about the clock of fpga I read spartan 6 clock resources but it was a bit unclear for me I just want to know when I entered a clock to a gclk pin of fpga and then I want to have for example 10 different frequency of the mother clock what should I do?how can use the pll of the FPGA and how many clock can I have from that gclk pin, if you have some simple files please send me.
Regards
Matin :)
 

barry

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You are confusing JTAG and slave/master serial.

First, I think you need to read the documentation.

For JTAG, there is no "master" device. You connect TMS and CLK to all the devices and TDO of the first device to TDI of the second one, etc.

As far as clocks, again, you need to read the documentation. No, you can't get 10 clocks out of a single PLL. Why do you need so many clocks? Can you just use dividers? It all really depends on your application.
 

ads-ee

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To clarify barry's answer for Q#1:

If you read the documentation...it states that JTAG has priority over all other configuration modes. The mode pins are not even looked at when JTAG takes over the configuration state machine.

matin-kh said:
2-if I want to use the fpga as a master and enter clock to other devices from fpga does it make any difference which pin is used as output?GCLK or IO pins? if it is make difference could you please tell me why?
Doesn't seem very confusing to me.
Xilinx UG382 said:
Spartan-6 FPGA Clocking Resources
UG382 (v1.10) June 19, 2015
Chapter 1:
Clock Resources
Clock Resources
The Spartan-6 FPGA clock resources consist of four types of connections:
• Global clock input pads (GCLK
GCLK has a dedicated input path to a global clock buffer, it is not a special output clock pad, because it is also a general purpose I/O pad so you can output a clock on it if you don't have any other pins available.

If you used clock dividers you could have 1 GCLK input and every other output pin on the device being an output clock. You wouldn't even need to use a DCM or PLL.

Your questions seem more like thought experiments instead of actual design requirements.
 
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