question about frequency compensation

[tanghua_0407]

hello everyone! I have a question about frequency compensation.
In the operation amplifier ,there are two poles :
p1=-1/R1C1
p2=-1/R2C2
always ,in the case that p1 is the first pole and p2 is the second pole,we can use miller compensation .
but if because of the large C load , p2 becomes the first pole ,how can I do??

 

[flatulent]

You are in trouble if the higher frequency pole can become near the lower frequency one. You can brute force the lower one lower but that reduces the closed loop bandwidth. You should decrease the output impedance of your amplifier to get the second pole r2c2 to not be such low a fequency.

 

[surianova]

hello everyone! I have a question about frequency compensation.
In the operation amplifier ,there are two poles :
p1=-1/R1C1
p2=-1/R2C2
always ,in the case that p1 is the first pole and p2 is the second pole,we can use miller compensation .
but if because of the large C load , p2 becomes the first pole ,how can I do??

If you drive the load that very big, for example a few hundred pF, it is better to use a buffer to drive the load( can use nmos buffer), so that it can isolate the load from the opamp.

1. let say the output impedence of buffer is 1/gm driving 100pF.

your pole frequeny become gm/100. (bandwidth increase)


2. If without buffer, let say output impedence Ro.

the pole frequency is 1/ 100(Ro) ( bandwidth reduce)

Hope this help


surianova

 

[wholx]

i think the solution could still be miller compensation. the miller compensation is applicable when the pole at the output and the pole at the input of the output stage are two dominant poles, no matter which is bigger.

 

[always@smart]

i think the solution could still be miller compensation. the miller compensation is applicable when the pole at the output and the pole at the input of the output stage are two dominant poles, no matter which is bigger.

Miller compensation might be the solution, it will shift two dominant pole, one towords the low frequency, another (output) pole to high frequency, so that the feedback circuit would not suffer significant gain drop (-40db/decade) within 180° phase.

 

[Btrend]

As I know, miller compensation need amplifier to provide a gain (A) , such that the miller cap can be increase to (1+A)Cm in the input of amplifier, and other one is (1+1/A)Cm in the output of amplifier.
But if ur load is dominated, how could u make it to become (1+A)Cload ?
in this case, there is no more gain stage to provide A.
Could u explain it more clearly ?

 

[wholx]

Btrend,
what you said makes sense. it seems Miller Compensation works only to make the interstage pole smaller and the output pole bigger. in case that the output pole is dominant and close to the interstage pole, the miller compensation just worsens the phase margin(~0).

let suppose CL is too big so that the output can be seen as AC ground, then the output stage gain A is almost 0. the interstage pole thus equals ωp2 = 1/Rin*(CGS+CGB+CGD), where Rin is the the output resistance of stage ahead.

in order to achieve a good phase margin, i think what we can do without adding new stage is to reduce the output resistance of ahead stage. this will reduce the gain of opamp. another solution is using a buffer to drive the big load, though this will reduce the noise rejection and increase the power dissipation. in this case, we need to recalculate the first two poles since the buffer's output resistance is small.