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Question about fanout in Altera Stratix II

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jzhangsun

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I want to implement a design with a alter stratix II , when i use the synplify pro
to synthesis my design, some nets have long delay due to them with big fanout (>100). then accoring to synplify reference manual, i apply the hard fanout limit to such nets ,but it doesnt work ,why? who can help me to resolve this question?
thanks
 

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Re: altera: fanout

In FPGA, the fanout is effectively achieved by routing buffers, thus the reported fanout number is not measuring a real load. Routing delays are basically unavoidable for larger designs.
 

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