Question about delta-sigma modulator's clock in frac-N PLL

[siboy]

frac modulator

In frac-N PLL frequency synthisizer, which signal should be the clock of the delta-sigma modulator, the Ref signal or the divided VCO signal? And why?
Thank you!

 

[andriclt]

noticed an old thread unanswered while posting my own.
I have seen PLLs using ref clock and feedback clock and both work equally well. Nothing wrong implementing it on way or the other since at steady state, reference clock & feedback clock have the same frequency. If you plan to use the feedback signal to clock the DSM, remember that the initial transient frequency of the divided clock will be away from target reference frequency. So be sure to synthesize the module and the ndivider interface for the range of frequency the feedback clock can assume. Also be wary of any startup issues using feedback clock - especially if your VCO is running at a very high frequency and your divider fails to respond at such high frequencies. With no feedback clock, the PFD will assume that the feedback clock is trailing the reference clock pushing the VCO to higher frequencies, causing instability. This will break the loop between DSM and feedback divider cauing you trouble.