Question about a clock pulse

[Finals]

I have just started VHDL class and is currently very raw regarding it. Forgive the noobness of my question.

Can a clock pulse be "1" at 0ns to 10ns?? If i made my design to assign an input signal to the output at rising edge, will it perform that function if the input is "1" during the duration of 0ns to 10ns if i set a rising edge at 0ns to 10ns?

Thanks in advance.

 

[balavinayagam]

you need to know about the delta delay in VHDL. actually VHDL is concurrent so if u assign

A <= B after 5 ns

then a transaction is scheduled to occur at 5 ns. but the event may occur or not depending on the previous value.

Now in vhdl there is an inherent delay known as delta delay after which every assignment will take place . this is to ensure the concurrency of operation. so if u assign a signal to any other then it will be assigned after that delta delay


for more reference read VHDL by Navabi

Added after 1 minutes:



for clk put

clk <= not clk after 10 ns


in a process . this will create a clock

 

[TrickyDicky]

Are you planning on creating real hardware or behavioural models?

If its the former, forget about lengths of time. things like clk < not clk after 10ns; cannot be synthesized into real hardware.

if its the latter, then you can easily do what balavinayagam suggested.

In answer to your question, the function rising_edge(clk) is only true in the single delta cycle when clock changes from 0 -> 1. This prevents clocked processes from triggering more than once during a clock period.