Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question about 2x clocking

Status
Not open for further replies.

gilazilla

Newbie level 2
Joined
Mar 24, 2008
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,298
Hi All,

I have a question about clocking.


I want to achieve "result 2".(see attachment) However i am having problem getting the correct system verilog to work.
I have no idea why it did not as expected. I keep on getting result 1 :(

Need some advice here.Thanks.

Each character is 5ns wide.

clkA 10101010
clkb 11110000
Result 1 AA00BB00
Result 2 AAAABBBB

I tried the following: both method dont work

1st try
task stretch (
input [3:0] value_A ,
input [3:0] value_B );


@(posedge clkB )
begin

module.data = value_A;

end


@(negedge clkB )
begin

module.data = value_B;

end



endtask : stretch


2nd try
task stretch (
input [3:0] value_A ,
input [3:0] value_B );


@(posedge clkA )
begin

module.data = value_A;
#10ns;
module.data = value_A;

end


@(posedge clkA )
begin

module.data = value_B;
#10ns;
module.data = value_B;

end



endtask : stretch
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top