Query regarding ternanry operations

[chris123@#]

Hi

I have a situation in system verilog

assign a = t ?b : 0;

t is initially 0. b is initially some data 0xC. After some time t changed to 1. b is still 0xC so "a" became 0xC. after some small delay, b changed to 0xD but "a" hasn't changed.
After further delay, t changed to 0 and a changed to 0.

I did not understand why "a" did not change to 0xD?

Any clarification on this would be very helpful

Thank you

 

[ThisIsNotSam]

what is "small delay"? do you have a testbench that shows this behavior?

 

[dpaul]

Please post your code and simulation results to get better answers.