hi ,
In my ASIC design, after finishing layout i checked for the timing,
the static timing analysis gave a results as follows,
setup slack => 3326 ps,
hold slack => 10 ps,
the target frequency of this design is 40MHZ(ie 25ns time period)
my doubt is that the hold slack margin 10ps is it enough,
else what range of values the hold slack margin should
be obtained in order to get timing safe,
which analysis you did ,
Single , Best case/Worst case , or OCV .
0.1ns is usually acceptable .
By the way what is your tecnology ( 0.18 or more/ less)
I thinks the hold time margin must be greater than 0.2 ns.
au_sun said:
hi ,
In my ASIC design, after finishing layout i checked for the timing,
the static timing analysis gave a results as follows,
setup slack => 3326 ps,
hold slack => 10 ps,
the target frequency of this design is 40MHZ(ie 25ns time period)
my doubt is that the hold slack margin 10ps is it enough,
else what range of values the hold slack margin should
be obtained in order to get timing safe,
hi ,
In my ASIC design, after finishing layout i checked for the timing,
the static timing analysis gave a results as follows,
setup slack => 3326 ps,
hold slack => 10 ps,
the target frequency of this design is 40MHZ(ie 25ns time period)
my doubt is that the hold slack margin 10ps is it enough,
else what range of values the hold slack margin should
be obtained in order to get timing safe,
Set Up slack is too much , please provide the following details,
are u doing "worst" case or "best" case analysis also tell me , what is your technology (0.18 or below) . your target freq is not high.
check the timing reports and confirm with designers.