sudarsv
Junior Member level 1
HI
I am trying to write a 2-process model code for vhdl. i have defined a few signals to establish communication. Process 1 (Master) sets the signal which triggers the Process 2 (slave). Now I am trying to reset the same signal in the slave process, but this does not seem to be working. Can you let me know how can I reset the signal in the slave process so as to save one extra clock pulse in the master.
Please note the signals are in the sensitivity list of the slave process
I am trying to write a 2-process model code for vhdl. i have defined a few signals to establish communication. Process 1 (Master) sets the signal which triggers the Process 2 (slave). Now I am trying to reset the same signal in the slave process, but this does not seem to be working. Can you let me know how can I reset the signal in the slave process so as to save one extra clock pulse in the master.
Please note the signals are in the sensitivity list of the slave process