vsrpkumar
Member level 4
I have some typical doubt.
I am developing a new ipcore for my company.
See the statements
case 1:
sensor_out={w_tdu_out};
w_dio_mux_out={w_tdu_out};
case2:
sensor_out={w_S};
w_dio_mux_out={w_tdu_out};
sensor_out is test ports for observing output in CRO/LA(oscilloscope)
w_dio_mux_out is connected to LEDs
in both case LED output differs but they drive same logic.I dont know whther FPGA P&R is inefficient.How to rectify this type of problems.I am using cyclone devive quartus II 5.1 s/w.
I am developing a new ipcore for my company.
See the statements
case 1:
sensor_out={w_tdu_out};
w_dio_mux_out={w_tdu_out};
case2:
sensor_out={w_S};
w_dio_mux_out={w_tdu_out};
sensor_out is test ports for observing output in CRO/LA(oscilloscope)
w_dio_mux_out is connected to LEDs
in both case LED output differs but they drive same logic.I dont know whther FPGA P&R is inefficient.How to rectify this type of problems.I am using cyclone devive quartus II 5.1 s/w.
