Queries : PFM mode Stability Analysis in DCDC converters.

[skamthey]

1. PFM mode loop is open loop or close loop?
2. Is it required to do Stability Analysis for PFM loop ? If No Why ?

 

[mtwieg]

1. PFM mode loop is open loop or close loop?
2. Is it required to do Stability Analysis for PFM loop ? If No Why ?

Depends on how you're trying to use PFM. In many cases it's just one possible way to modulate duty cycle, and doesn't really have any impact on the state space averaged models.

 

[crutschow]

A DC-DC converter is usually closed-loop, PFM or otherwise (do you mean PWM which is the typical control method?).

Normally you need to do an analysis of the stability of any closed-loop control circuit.

 

[skamthey]

Depends on how you're trying to use PFM. In many cases it's just one possible way to modulate duty cycle, and doesn't really have any impact on the state space averaged models.

Please explain in terms of stability analysis. That will be helpful .

- - - Updated - - -

A DC-DC converter is usually closed-loop, PFM or otherwise (do you mean PWM which is the typical control method?).

Normally you need to do an analysis of the stability of any closed-loop control circuit.

Yes, for PWM mode Stability analysis is required. Please explain the necessity of stability analysis in PFM loop.

 

[mtwieg]

Please explain in terms of stability analysis. That will be helpful .

I'm not really sure how else to say it. All duty cycle modulation schemes (fixed frequency pwm, constant off time, constant on time, pfm) boil down to the control of ton and toff, and therefore duty cycle, for the purpose of state space averaging anyways. After that is accounted for, analysis is the same as it would be for any other modulation scheme. For info on state space averaging you should read this classic paper: https://www.ee.bgu.ac.il/~kushnero/temp/guamicuk.pdf

 

[FvM]

No system has been actually presented. How can we know if the imagined design is open or closed loop? It's a matter of topology rather than modulation method.

 

[skamthey]

No system has been actually presented. How can we know if the imagined design is open or closed loop? It's a matter of topology rather than modulation method.

I didn't get your point. "System is not present" means what ?
PFM loop consist of: Res div feedback, Max current detect block, Zero current detect block, Comparators along with PowerFets, L & C etc.
Please Consider PFM loop as closed loop. Correct me if I am wrong.

 

[mtwieg]

I didn't get your point. "System is not present" means what ?

It means you should only expect an answer as specific as your question, and your question is extremely vague.

PFM loop consist of: Res div feedback, Max current detect block, Zero current detect block, Comparators along with PowerFets, L & C etc.
Please Consider PFM loop as closed loop. Correct me if I am wrong.

If you're looking for help doing specific analysis, then you should give a detailed schematic at least.

 

[skamthey]

I got answers up-to some extent, sharing for others.

1. PFM mode loop is open loop or close loop?
Ans: Close Loop.

2. Can we model the PFM loop?
Ans: Yes, we can model the PFM loop using state-space averging method. Its bit complex as involved algebra.

3. Is it required to do Stability Analysis for PFM loop ? If No Why ?
Ans: Yet to find the answer.

Peoples are welcome to provide their views on 3rd question.