Quartus JTAG ID Error using an EPM7128SLC84-7 on PLDT-2 DB

[Gerry_robotics]

pldt id format

Hi Everyone,

I am a Rookie at this, I just started playing around with Quartus and my old ALtera PLDT-2 board, so you'll have to understand my limited knowlege of this amazing and wonderfull world of EPLD's.

My problem lies with a JTAG ID error.

I have successfully been able to program with Quartus II v5.1 on my PLDT-2 Development board using an Altera EPM7128SLC84-10 chip so I know that my hardware works along with Quartus, but when I try to program these other chips I got off Ebay, the Altera EPM7128SLC84-7, I recieve the following error:

Error: JTAG ID code specified in JEDEC STAPL Format File does not match any valid JTAG ID codes for device

All 25 chips I have seem to be configured the same, the 7 Seg display & LED's light up identical to one and other when power is applied.

I read on different sites that the JTAG ID's for the devices might have to be reset or enabled with a MPU? Is this the case? or is there a way I can do it on my own with the PLDT-2 board? or rigging up my own interface somehow?

If I have to get an MPU, where do I get one that can reprogram my load of EPM7128SLC84-7 chips, I hope I can salvage these somehow.

Any advice will be greatly appreciated.


Thanks for your time Everyone.

Kind Regards,
Gerry O"Brien
robotics@digital-circuitry.com

 

[shawndaking]

jtag error code 7

use maxplus2 , i'm surprised that you actually managed to program it with quartos.

tyy one of the late versions like 10.23

 

[FvM]

series 2 jtag id code

Hello,

JTAG ID error means, that the ID read from the part doesn't match the ID for the selected part from the device database. The part ID can't be changed, it is an unique combination of manufacturer and type ID. Typically the issue happens cause you selected the wrong part. The ID read from JTAG is displayed with a Scan Chain action, you can analyze what kind of discrepancy exists.

Regards,
Frank

 

[Gerry_robotics]

Hey again Folks,

I just wanted to make a quick reply to this old thread I made back in 08 regarding the Altera MAX7000 JTAG Issue.

Since my last post I have acquired a couple of Key pieces of Equipment that essentially solved this JTAG communication problem.

I acquired a DATA I/O "LabSite" Universal Programmer with the 84Pin CPLD adapter off eBay. I then eventually found the matching software for this module after months of pain staking research and searching through Forums. Unit is Shown Below:

And now just recently, I acquired the Altera LP6 "Logic Programming card" for the vintage Altera PL-ASAP2 MPU setup. This package contains an Adapter Base that accommodates various Chip socket adapters. This MPU Base interfaces to the LP6 ISA card via a DB25 Pin Ribbon cable and programs your chip of choice using the Altera MAXPLUS2 Stand Alone Programmer software.

The Altera MPU Base.

Below are a couple of the Adapters I have acquired:

So here it is in a nutshell:

EPLD's like the Altera 7128SLC84 have JTAG programming communication inputs also referred to as ISP communication. The Designer or programmer also has the option to have these JTAG inputs be converted to I/O lines for interfacing once the programming of the chip is completed. This therefore disconnects the JTAG input lines and the chip can no longer be re-programmed with a JTAG programming board, or through ISP (in Service programming); which unfortunately is what most 150 dollar range Altera college and university development boards use. This JTAG error occurs due to the fact that the JTAG port on the Chip is simply disabled. The chip is not actually faulty or damaged at all, which many users are lead to believe.

This is a common problem many student/hobbyists encounter when they buy second hand Chips off the net like Ebay. The chips are useless as far as JTAG
programming goes. The only way to have the JTAG communication lines restored is to use a NON-JTAG programmer Like the Altera Master Programming unit or a third party programmer like the DATA I/O Labsite or Unisite. Using these programmers to erase the chips or perform a Blank-Check function, reconnects and enables the JTAG communication port just as they are when you first purchase the chips new.

This particular mode for the Altera chips is called "JTAG LOCKOUT". and is just a real pain in the butt.

But the issue is now solved Finally after over a year of researching this
problem. I actually received the software for my Labsite unit from a user in another forum that had it on an old 386 computer hard drive in his basement. What are the chances of that!

And just over the past few weeks.... I now have the Altera Master Programming Unit "PL-ASAP2" up and running also. Interfaced with the LP6 Logic programming card and running with the MAXPlus2 software.

Needless to say with this new Gear, I was able to restore all of my JTAG Locked Altera chips.

In any case, I just wanted to share that intel with all of you.




Kind Regards,
Gerry O'Brien

P.S.
Below are some links to Yahoo Groups I opened up specifically for Altera and DATA I/O Programming Hardware. Enjoy!

**broken link removed**

AlteraMAX7000 : Altera MAX 7000 Family CPLD Programming