[Quartus II] How to hold a process for a specific time

[aeneas81]

Hi all,
How can I check that a signal holds it's value for a specific period, such as 5ms, using VHDL in Quartus II?
I tried to use Wait for, after simulation, that doesn't has any effect at all. Hope that any of you would be able to help. Thanks in advance

Rgds,
aen

 

[r_e_m_y]

Hi,

I don't understand what is your problem ...

Do you try to hold a signal in a synthesisable vhdl code with a wait for statement ? This is not possible. You hav to creater a counter and count the correct number of global clock edges...

Do you try to see in simulation under Quartus if the internal signal you have built is stable for 5 ms ? you just configure your waveform window with the selected signal have look at the simulation result ...

If this is not the purpose of your demand, please detail

 

[wasp]

you need signal change state detect circuit and delay counter.
for example:
-- d - input signal
------------------------------------------------------
-- flip-flop for delay signal
------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
--------------------------------------------------------
-- change_state ='1' when input singal change state from 1->0 or 0 ->1
--------------------------------------------------------
change_state <= d xor q;
---------------------------------------------------------
-- Gotcha and hold event of signal change state
---------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if rst ='1' then
flag <='0';
elsif ce = '1' then
flag <= change_state;
end if;
end if;
end process;
ce <= not flag;
-------------------------------------------------------
-- next simple fsm which control few conditions
-- cnt - delay counter
-------------------------------------------------------
process(state,cnt,flag)
begin
case state is
when s0 =>
if cnt = end_of_5ms_period then
if flag = '1' then
nstate <= s1; -- signal change state during 5 ms
-- period
else
nstate <= s2; -- all ok signal idle during 5ms
end if;
else
nstate <= s0; --wait end of 5 ms period
when s1 => ....
when s2 => ....
.....
end case;
end process;

 

[aeneas81]

[qu@rtus II] How to hold a process for a specific time

wow, thanks for the code, wasp. i've tried using the counter version as mentioned by r_e_m_y, though it works fine, I am just wondering is there any other option to achieve the same thing, using less code. anyway, thanks a lot.

 

[lucbra]

I shouldn't worry about the number of lines of code you have to write. Thing is that every method will consume a number of flip-flops, depending on the master clock. This number is fix.