Quartus II Cyclone II - RAM using Mega Core

[Rushdiey]

I got some assignment but i dont understand what it need
I already doing some research i think my project not about the block ram right?
The problem is how i can put my previous coding into ram
Auto Execution of ALU Operations
Load all ALU operations into RAM (use Mega Core).
Read Input Data from Switches
ALU Sequential will execute OPCODE from RAM 1
ALU Concurent will execute OPCODE from RAM 2
Show input and result on LCD

I already done 1st assignment which is i need to display alu concurent and sequntial at lcd
Im using quartus cylcone II

 

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I'm not entirely sure what you are trying to ask, but it seems like you don't know how to initialize a block ram in altera?

Use a MIF file see this and this.

 

[Rushdiey]

I'm not entirely sure what you are trying to ask, but it seems like you don't know how to initialize a block ram in altera?

Use a MIF file see this and this.

Ya using mif file.. But how to ALU in that ram?

 

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Your first post says the ALU will have the opcodes in the RAM. You write a mif file with the opcodes according to what you are supposed to calculate. All you then do is use a counter to address the RAM producing the opcodes at the output, which are then input to the ALU to do the calculations.

 

[Rushdiey]

Your first post says the ALU will have the opcodes in the RAM. You write a mif file with the opcodes according to what you are supposed to calculate. All you then do is use a counter to address the RAM producing the opcodes at the output, which are then input to the ALU to do the calculations.

About mif file.. Is it coding? My lecturer said we should use that

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Okay i know what is mif. Sorry

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AFter i do tthat
The next step is wat?

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Im stuck here. Dont know what to do next step

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I already can read my mif file.
So how about to write the data into ram

 

[FvM]

Start with a complete problem description. What's the intended function of the ALU, input and output signals, etc.

The VHDL snippet gives an idea of the function, but the data width isn't specified. How's the 32x4-bit RAM related to it?

Initializing a RAM with a mif file suggests that you want to use it as ROM rather than RAM.

 

[Rushdiey]

32x4 for read 32x8 for write

 

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32x4 for read 32x8 for write

This is hardly a complete problem description that was asked for in #6.

All I can assume now is you don't know what you are supposed to do at all. Maybe you should go ask the class instructor about this instead of asking us.

FYI, we aren't paid to teach you, the instructor of your class though is getting paid to do so. If they are unwilling to teach you anything, maybe you should rethink which school you are spending money with.:thinker:

 

[Rushdiey]

I dont know how to explain it
Because my english very bad.
Later i give u detail about it

 

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Auto Execution of ALU Operations
Load all ALU operations into RAM (use Mega Core).
Read Input Data from Switches
ALU Sequential will execute OPCODE from RAM 1
ALU Concurent will execute OPCODE from RAM 2
Show input and result on LCD

If this was the problem description given by your instructor then, you've got the answer for loading the ALU operation into ROM using a mif file to initialize a RAM with the opcode sequence (the auto execution of ALU operations)

Two RAM/ROMs and two ALUs (the code posted as a picture).

You already said you have the input data stuff (assumed because of the next statement...) and the display ALU results on LCD.

So what is the problem? All you have to do is create a top level HDL file that has each of these parts instantiated, instead you keep asking about the RAM or posting about the RAM size/width. I get the distinct feeling this is your very first experience trying to applying your knowledge to something practical. :???: