Quartus compilation too slow for RAM design.

[sora5563]

when using quartus tools to compile the correction of my Dual port RAM design,
it takes me hours to compile and synthesize the source code file.

The RAM with only the size of 64 bytes, successful compile after 5 minutes.
The times increase linearly when the size of the RAM double,
let's say 128bytes takes about 10minutes or more, so on.

Im going to design 4 kbytes RAM myself with my small project. Everything is
pretty good except the RAM with the compilation times consume hours of time.

That's pretty unhappy.

************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity RAM128 is
generic (
A: integer := 7;
WORDS: integer := 128;
M: integer := 8
);
port (
clk : in STD_LOGIC;
TxR : in STD_LOGIC;
TxW : in STD_LOGIC;
AddrTx1 : in STD_LOGIC_VECTOR(A-1 downto 0);
AddrTx2 : in STD_LOGIC_VECTOR(A-1 downto 0);
DataTxIn : in STD_LOGIC_VECTOR(M-1 downto 0);
DataTxOut : out STD_LOGIC_VECTOR(M-1 downto 0);
AddrRx1 : in STD_LOGIC_VECTOR(A-1 downto 0);
AddrRx2 : in STD_LOGIC_VECTOR(A-1 downto 0);
RxW : in STD_LOGIC;
RxR : in STD_LOGIC;
DataRxIn : in STD_LOGIC_VECTOR(M-1 downto 0);
DataRxOut : out STD_LOGIC_VECTOR(M-1 downto 0)
);
end RAM128;

architecture RAM128_arch of RAM128 is

subtype cell is std_logic_vector(M-1 downto 0);
type ramArray is array (0 to WORDS-1) of cell;
signal ram: ramArray;
signal AddrMatch :std_logic;

begin
AddrMatch <= '1' when (AddrTx1 = AddrRx2) else '0';

process(clk, AddrTx1, AddrRx2, TxW, RxW, AddrMatch)
begin
if (clk'event and clk = '1')then
if (TxW = '1') and (AddrMatch = '0')then
ram(CONV_INTEGER(unsigned(AddrTx1))) <= DataTxIn;
else
if (TxW = '1') and (AddrMatch = '1') and (RxW = '1') then
ram(CONV_INTEGER(unsigned(AddrTx1))) <= DataTxIn;
end if;
end if;

if (RxW = '1') and (AddrMatch = '0')then
ram(CONV_INTEGER(unsigned(AddrRx2))) <= DataRxIn;
else
if (TxW = '1') and (AddrMatch = '1') and (RxW = '1') then
ram(CONV_INTEGER(unsigned(AddrTx1))) <= DataTxIn;
end if;
end if;
end if;
end process;

process(RxR, AddrRx1, ram)
begin
if (RxR = '1')then
DataRxOut <= ram(CONV_INTEGER(unsigned(AddrRx1)));
else
DataRxout <= (others => '0');
end if;
end process;

process(TxR, AddrTx2, ram)
begin
if (TxR = '1')then
DataTxOut <= ram(CONV_INTEGER(unsigned(AddrTx2)));
else
DataTxOut <= (others => '0');
end if;
end process;

end RAM128_arch;
******************************************************************

Did any experts there can help to tackle this problem?
Did any good ideas there to reduce the time of compilation ?
This makes me crazy!
Please help to post your appreciatable ideas!!!

 

[alt007]

hi dear ,
1. use smart comilation option.
2. Increase RAM upto 1 GB OF OUR WORK STATION


ALT007

Added after 40 seconds:

hi dear ,
1. use smart comilation option.
2. Increase RAM upto 1 GB OF OUR WORK STATION


ALT007

 

[sora5563]

Thanx, but i have to run full compilation first right, bcuz smart compilation is
a recompilation option, it skips any unchangeable module during compilation.

If i dun want to upgrade RAM of my computer,
Is there another ways to increase the speed of compilation?