dipin
Full Member level 4
hi,
iam using quartus prime 16.0
in my module ,,i got 3 signals in conduit interface and iam declaring 3 of them as(signal type) "export" ..but then following error is coming..
then i rename the 3 signals to
export1, export2, export3
then the error is gone but when i generate HDL file
which is i declared earlier in conduit...so this is the problem with conduit interface decleartion..
when i try to edit the module i declared in qsys there is only one signal in conduit interface
anybody know how to remove this particular problem. any help is really appreciated
thanks and regards
update ..............
i am using cyclone 5 fpga (de0_nano_soc)...
and cyclone v hard processor as hps
iam using quartus prime 16.0
in my module ,,i got 3 signals in conduit interface and iam declaring 3 of them as(signal type) "export" ..but then following error is coming..
Error: There are multiple signals with role "export". Components using hw.tcl package 14.0 and greater must specify unique signal roles.
while executing "add_interface_port conduit_end slower export Input 1"
then i rename the 3 signals to
export1, export2, export3
then the error is gone but when i generate HDL file
Error (12002): Port "delay_ctrl_delay" does not exist in macrofunction "soc"
Error (12002): Port "delay_ctrl_faster" does not exist in macrofunction "soc"
Error (12002): Port "delay_ctrl_slower" does not exist in macrofunction "soc"
which is i declared earlier in conduit...so this is the problem with conduit interface decleartion..
when i try to edit the module i declared in qsys there is only one signal in conduit interface
anybody know how to remove this particular problem. any help is really appreciated
thanks and regards
update ..............
i am using cyclone 5 fpga (de0_nano_soc)...
and cyclone v hard processor as hps
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