hi,
1. memory of viterbi decoder depends on trace back length.
2. suppose for 1/2 encoder, constraint length =3. if u give 100 bit data when we encode u will get 200 bit output. ie 100 pairs
3. now u transmit that data and viterbi dec has to decode it.
4. here the problem araises ie, you need to wait for 100 clk cycles to get your data.
and the memeory registers are ex say for each cycle u need 4 registers to store data taotal u need 400 registers. which will cost u more.
5. so a thumb rule is u can decode the data after 5 times the constraint length
with little performance degradation.
so here k=3, if u deocde after 3x5=15 ie at every 15 cycle. ex u will have error of 20 bits in ur 100 bit.
if you decode after 30 cycle you get only 15 errors.
'' 50 cycle 13 errors
" 100 2 errors.
so as you increase your depth you will get better performance.
i had implemented hard and soft decision vd in verilog. if u have any further clarification you can mail me at
cmangaraju@gmail.com