Q: How To Handle the Special Cases in I2C Bus Arbitration?

[frankrick]

Well, I have one question about I2C bus arbitration: how to deal with the special cases of arbitration as mentioned on page 13 of I2C-bus specification? In my current design the logic simply performs the arbitration during the data/address transfer phase, not covering the START/STOP conditions. Is it good enough? Or the arbitration shall be implemented as robust as possible? I think the I2C specification doesn't describe this problem clearly so that each vendor may have their own solutions to handle it.

Any comment will be appreciated!

p.s. The section 8.2 in I2C spec looks weird.... it seems that the spec admitted that the special cases are possible to occur, but the spec said nothing to deal with them

 

[yln2k2]

Re: Q: How To Handle the Special Cases in I2C Bus Arbitratio

Hi ,


Design should comply with the specification .

So what ever spec support designer need to implement the same .


Thanks & Regards
yln

 

[frankrick]

Re: Q: How To Handle the Special Cases in I2C Bus Arbitratio

Hi ,

Design should comply with the specification .
So what ever spec support designer need to implement the same .

Thanks & Regards
yln

Well, the question is, I2C spec did mention the special cases of the arbitration, but said nothing about the solution. More detailedly, the spec admitted that "it is possible for such a situation occur...". However it also said "In other words, arbitration isn't allowed between...". Isn't it a little bit weird?

If a MASTER is generating a repeated START condition to a SLAVE and another MASTER is sending a data bit to the same SLAVE at the same time, then the arbitration logic stops working at the moment?