Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PWM using AXI TIMER core in EDK

Status
Not open for further replies.

mano1988

Newbie level 5
Newbie level 5
Joined
Feb 12, 2013
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Coimbatore, India
Visit site
Activity points
1,338
Hi,

Am using SPARTAN6-LX9 FPGA and trying to generate PWM (2 nos) signals from my embedded processor system (microblaze). Also am using Xilinx 13.2-embedded edition.
I found the AXI Timer core in the IP catalog. I have integrated it to my processor and generated a PWM signal using the timer (PWM is generated from the PWM module in the timer by configuring the TCSR & TLR).

Now I want an another PWM signal that is just not(invert) of the first PWM signal. How do I achive it?

Is there any way I could instantiate a NOT gate or simalr function in the microblaze?

Thank You,
Manoj
 

Not sure how much you are "changing" your embedded system...you could just open the top level of the embedded system RTL and edit the file so you generate the PWM_N = not(PWN); output. If you do this every time you make changes to the embedded system you'll have to reapply the edits. You might want to make a script to do that.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top