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# PVT corners for timing analysis

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#### logicdive

##### Newbie
Hello,

this is a basic question. I am trying to understand better timing requirements for building digital circuits e.g. 800 MHz clock frequency.
1) What simple circuit could be simulated that would meet this frequency? (I would like to build a spice netlist, e.g. logic + flip flop)?
2) How do timing corners of flipflop impact the timing?
3) how can the SS,FF,TT corners be seen in this circuit?

Thanks for suggestions and ideas!

#### dpaul

The basic digital blocks you build might not show a problem 800M clock . But in a million gate design passing timing at this clock might be an issue and it entirely depends on how the high level design is structured/created.

##### Super Moderator
Staff member
e.g. 800 MHz clock frequency.
1) What simple circuit could be simulated that would meet this frequency?

If you want a multivibrator based on an RS flip-flop, there's the classic astable made from 2 transistors, 2 capacitors and 4 resistors. To obtain 800 MHz a sensible capacitor value is 1 pF.

There's also a pulse generator made with 2 invert-gates, 1 cap and 1 resistor.

Watch the waveforms to see where volt levels start to change slightly and lead up to a transition.

These are simple circuits. It's easy for a simulator to make these work at 800 MHz since it uses ideal components...
Unless you choose component models that are lifelike. Even then you may or may not observe the characteristics you refer to.

#### ThisIsNotSam

Hello,

this is a basic question. I am trying to understand better timing requirements for building digital circuits e.g. 800 MHz clock frequency.
1) What simple circuit could be simulated that would meet this frequency? (I would like to build a spice netlist, e.g. logic + flip flop)?
2) How do timing corners of flipflop impact the timing?
3) how can the SS,FF,TT corners be seen in this circuit?

Thanks for suggestions and ideas!
make a flop-inverter-inverter-...-inverter-flop circuit
modulate the number of inverters until you get a period that is about 1ns, 1ghz frequency
the timing will change for the corners if you do spice simulations, this is going to become very evident very quickly
you will also see that the setup and clk-to-q delay of the flop will change for different corners

logicdive

### logicdive

Points: 2

#### dick_freebird

If you want to create a worthy "challenge case" then
you want something like a flip-flop with feedback
logic. This emulates a register-register path with
some relevant logic, like a useful sequential circuit.
The logic should represent a reasonable worst case
(i.e. a case which you would insist that synthesis
can handle without you designing a faster cell
library that you've got).

Now test that at a series of ascending clock
frequencies until the logic state passes through
stretched-delay, to metastable, to failed. Take
the last passing clock-rate and subtract some
design margin based on what you know about
model coverage of foundry-shipped reality.

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